 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320DM6441 Datasheet(PDF) 28 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM6441 Datasheet(HTML) 28 Page - Texas Instruments |
|
|
28 / 229 page  www.ti.com TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE(1) OTHER(2) DESCRIPTION NAME NO. EM_A[8]/ This pin is multiplexed between EMIFA and GPIO. N3 I/O/Z DVDD18 GPIO23 For EMIFA, it is address bit 8 output EM_A[8]. EM_A[7]/ This pin is multiplexed between EMIFA and GPIO. N2 I/O/Z DVDD18 GPIO24 For EMIFA, it is address bit 7 output EM_A[7]. EM_A[6]/ This pin is multiplexed between EMIFA and GPIO. N1 I/O/Z DVDD18 GPIO25 For EMIFA, it is address bit 6 output EM_A[6]. EM_A[5]/ This pin is multiplexed between EMIFA and GPIO. K3 I/O/Z DVDD18 GPIO26 For EMIFA, it is address bit 5 output EM_A[5]. EM_A[4]/ This pin is multiplexed between EMIFA and GPIO. K4 I/O/Z DVDD18 GPIO27 For EMIFA, it is address bit 4 output EM_A[4]. EM_A[3]/ This pin is multiplexed between EMIFA and GPIO. K2 I/O/Z DVDD18 GPIO28 For EMIFA, it is address bit 3 output EM_A[3]. This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. EM_A[2]/ In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0 (CLE)/ J1 I/O/Z DVDD18 determine if address, data, or control information is being transmitted between an HCNTL0 external host and DM6441. EM_A[1]/ This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. (ALE) J2 I/O/Z DVDD18 In HPI mode, it is half-word identification input HHWIL. HHWIL This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For EMIFA, this is address output EM_A[0], which is the least significant bit on a 32-bit word address. EM_A[0]/ When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the DA2/ J4 I/O/Z DVDD18 address. HCNTL1/ For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. GPIO53 For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine if address, data, or control information is being transmitted between an external host and DM6441. Device Overview 28 Submit Documentation Feedback |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
