TMS320DM6441 datasheet(71/229 Pages) TI

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TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing

Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19

and Table 3-20. Enabling PWM2, PWM1, CCD, and LCD functionality overrides the RGB modes. RGB666

interface pin functionality requires setting the RGB666 PINMUX0 register bit field to ‘1’ and PINMUX1

Table 3-19. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS

MULTIPLEXED PINS

PWM2/

PWM1/

C_FIELD/

LCD_FIELD/

RGB888

RGB666

PWM2

PWM1

CFLDEN

LFLDEN

B2/

R2/

R0/

B0/

GPIO[47]

GPIO[46]

GPIO[4]

GPIO[3]

GPIO[47]

GPIO[46]

GPIO[4]

GPIO[3]

LCD_FIELD

C_FIELD

PWM1

PWM2

GPIO[4]

GPIO[3]

Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS

MULTIPLEXED PINS

R1/

B1/

G1/

G0/

RGB888

PWM2

PWM1

CFLDEN

LFLDEN

GPIO[38]

GPIO[6]

GPIO[5]

GPIO[2]

GPIO[38]

GPIO[6]

GPIO[5]

GPIO[2]

3.5.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin

functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and

control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only

allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in

conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1

if the buffer is not being used (i.e. for compact flash). This multiplexing is shown in Table 3-22. When

ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be

used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA

buffers drive away from DM6441 and don’t cause bus contention with the EMIFA. Note that switching

between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus

contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA

requests have completed before clearing the ATAEN bit.

Table 3-21. ATA, EMIFA, and GPIO Pin Multiplexing Control

PINMUX0

MULTIPLEXED PINS

BIT FIELD

EM_BA[1]/

EM_A[0]/

EM_D[15:0]/

GPIO[50]/

GPIO[51]/

EM_R/W

EM_BA[0]/

RDY/BSY/

DIOR/

DIOW/

ATAEN

GPIO[52]/

GPIO[53]/

DD[15:0]

ATA_CS0

ATA_CS1

INTRQ

ATA0

EM_WAIT

EM_OE

EM_WE

ATA1

ATA2

GPIO[50]

GPIO[51]

EM_R/W

EM_BA[0]

RDY/BSY

EM_OE

EM_WE

EM_BA[1]/

EM_A[0]/

EM_D[15:0]

GPIO[52](1)

GPIO[53](1)

ATA_CS0

ATA_CS1

INTRQ

ATA0

EM_WAIT

DIOR

DIOW

ATA1

ATA2

DD[15:0]

(1)

This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

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