56F8037 datasheet(91/180 Pages) FREESCALE

91 / 180 page

56F8037 Data Sheet, Rev. 2

Freescale Semiconductor

Preliminary

6.3 Register Descriptions

A write to an address without an associated register is an NOP. A read from an address without an

associated register returns unknown data.

Table 6-1 SIM Registers (SIM_BASE = $00 F100)

Acronym

Base Address +

Section

Location

CTRL

Control Register

6.3.1

RSTAT

Reset Status Register

6.3.2

SWC0

Software Control Register 0

6.3.3

SWC1

Software Control Register 1

6.3.3

SWC2

Software Control Register 2

6.3.3

SWC3

Software Control Register 3

6.3.3

MSHID

Most Significant Half of JTAG ID

6.3.4

LSHID

Least Significant Half of JTAG ID

6.3.5

PWR

Power Control Register

6.3.6

Reserved

CLKOUT

CLKO Select Register

6.3.7

PCR

Peripheral Clock Rate Register

6.3.8

PCE0

Peripheral Clock Enable Register 0

6.3.9

PCE1

Peripheral Clock Enable Register 0

6.3.10

SD0

Stop Disable Register 0

6.3.11

SD1

Stop Disable Register 1

6.3.12

IOSAHI

$10

I/O Short Address Location High Register

6.3.13

IOSALO

$11

I/O Short Address Location Low Register

6.3.14

PROT

$12

Protection Register

6.3.15

GPSA0

$13

GPIO Peripheral Select Register 0 for GPIOA

6.3.16

GPSA1

$14

GPIO Peripheral Select Register 1 for GPIOA

6.3.17

GPSB0

$15

GPIO Peripheral Select Register 0 for GPIOB

6.3.18

GPSB1

$16

GPIO Peripheral Select Register 1 for GPIOB

6.3.19

GPSCD

$17

GPIO Peripheral Select Register for GPIOC and GPIOD

6.3.20

IPS0

$18

Internal Peripheral Source Select Register 0 for PWM

6.3.21

IPS1

$19

Internal Peripheral Source Select Register 1 for DACs

6.3.22

IPS2

$1A

Internal Peripheral Source Select Register 2 for Quad Timer A

6.3.23

Reserved

56F8037 Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

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