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56F8037 Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc |
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56F8037 Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc |
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98 / 180 page ![]() 56F8037 Data Sheet, Rev. 2 98 Freescale Semiconductor Preliminary 6.3.8 Peripheral Clock Rate Register (SIM_PCR) By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it. Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured. Figure 6-9 Peripheral Clock Rate Register (SIM_PCR) 6.3.8.1 Quad Timer B Clock Rate (TMRB_CR)—Bit 15 This bit selects the clock speed for the Quad Timer B module. • 0 = Quad Timer B clock rate equals the system clock rate, to a maximum 32MHz (default) • 1 = Quad Timer B clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14 This bit selects the clock speed for the Quad Timer A module. • 0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default) • 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13 This bit selects the clock speed for the PWM module. • 0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default) • 1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.4 Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12 This bit selects the clock speed for the I2C run clock. •0 = I2C module run clock rate equals the system clock rate, to a maximum 32MHz (default) •1 = I2C module run clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.5 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRB_ CR TMRA_ CR PWM_ CR I2C_ CR 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 0 0 0 000 0 0 0 0 0 0 0 0 0 0 |
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