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OPA875 Datasheet(PDF) 11 Page - Texas Instruments |
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OPA875 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 18 page ![]() www.ti.com OPERATING SUGGESTIONS DRIVING CAPACITIVE LOADS DESIGN-IN TOOLS DEMONSTRATION FIXTURES MACROMODELS AND APPLICATIONS DC ACCURACY OPA875 SBOS340 – DECEMBER 2006 Results for n varying from 2 to 6 are given in Table 2. Table 2. Series Resistance versus Number of Parallel Outputs One of the most demanding, yet very common load conditions is capacitive loading. Often, the capacitive NUMBER OF OPA875s RO (Ω) load is the input of an ADC—including additional 2 69 external capacitance that may be recommended to 3 63.94 improve ADC linearity. A high-speed device such as 4 59.49 the OPA875 can be very susceptible to decreased 5 55.59 stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. 6 52.15 When the device open-loop output resistance is considered, this capacitive load introduces an The two major limitations of this circuit are the device additional pole in the signal path that can decrease requirements for each OPA875 and the acceptable the phase margin. Several external solutions to this return loss because of the mismatch between the problem have been suggested. When the primary load (75 Ω) and the matching resistor. considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This isolation resistor does not A printed circuit board (PCB) is available to assist in eliminate the pole from the loop response, but rather the initial evaluation of circuit performance using the shifts it and adds a zero at a higher frequency. The OPA875. The fixture is offered free of charge as an additional zero acts to cancel the phase lag from the unpopulated PCB, delivered with a user's guide. The capacitive load pole, thus increasing the phase summary information for this fixture is shown in margin and improving stability. Table 3. The Typical Characteristics show the recommended Table 3. OPA875 Demonstration Fixture RS versus capacitive load and the resulting frequency response at the load; see Figure 5. ORDERING LITERATURE PRODUCT PACKAGE NUMBER NUMBER Parasitic capacitive loads greater than 2pF can begin OPA875IDGK MSOP-8 DEM-TIV-MSOP-1A SBOU044 to degrade the performance of the OPA875. Long PCB traces, unmatched cables, and connections to OPA875ID SO-8 DEM-TIV-SO-1A SBOU045 multiple devices can easily cause this value to be The demonstration fixture can be requested at the exceeded. Always consider this effect carefully, and Texas Instruments web site at (www.ti.com) through add the recommended series resistor as close as the OPA875 product folder. possible to the OPA875 output pin (see the Board Layout Guidelines section). SUPPORT Computer simulation of circuit performance using The OPA875 offers excellent DC signal accuracy. SPICE is often useful when analyzing the Parameters that influence the output DC offset performance of analog circuits and systems. This is voltage are: particularly true for video and RF amplifier circuits • Output offset voltage where parasitic capacitance and inductance can • Input bias current have a major effect on circuit performance. A SPICE • Gain error model for the OPA875 is available through the Texas • Power-supply rejection ratio Instruments web site at www.ti.com. These models do a good job of predicting small-signal AC and • Temperature transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. 11 Submit Documentation Feedback |
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