OPA875 datasheet(13/18 Pages) TI

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BOARD LAYOUT GUIDELINES

e =

e +(i R ) +4kTR

(7)

THERMAL ANALYSIS

P =10Vx11mA+(5 [4x(100

||804 ) ] )=180mW

MaximumT =+85 C+(0.18mWx140°C/W)=110°C

OPA875

SBOS340 – DECEMBER 2006

Dividing this expression by the device gain (2V/V)

gives the equivalent input-referred spot noise voltage

Achieving

optimum

performance

with

high

at the noninverting input as shown in Equation 7.

frequency amplifier such as the OPA875 requires

careful attention to board layout parasitics and

external component types. Recommendations that

will optimize performance include:

Evaluating these two equations for the OPA875

circuit and component values shown in Figure 30

a) Minimize parasitic capacitance to any AC

gives a total output spot noise voltage of 13.6nV/

√Hz

ground for all of the signal I/O pins. Parasitic

and a total equivalent input spot noise voltage of

capacitance on the output pin can cause instability:

6.8nV/

√Hz. This total input-referred spot noise

on the noninverting input, it can react with the source

voltage is higher than the 6.7nV/

√Hz specification for

impedance to cause unintentional bandlimiting. To

the mux voltage noise alone. This number reflects

reduce unwanted capacitance, a window around the

the noise added to the output by the bias current

signal I/O pins should be opened in all of the ground

noise times the source resistor.

and power planes around those pins. Otherwise,

ground and power planes should be unbroken

elsewhere on the board.

Heatsinking or forced airflow may be required under

b) Minimize the distance (< 0.25") from the

extreme operating conditions. Maximum desired

power-supply

pins

high

frequency

0.1

µF

junction temperature will set the maximum allowed

decoupling capacitors. At the device pins, the

internal power dissipation as discussed in this

ground and power plane layout should not be in

document. In no case should the maximum junction

close proximity to the signal I/O pins. Avoid narrow

temperature be allowed to exceed +150

°C.

power and ground traces to minimize inductance

between the pins and the decoupling capacitors. The

Operating junction temperature (TJ) is given by TA +

power-supply connections (on pins 9, 11, 13, and 15)

PD × θJA. The total internal power dissipation (PD) is

should always be decoupled with these capacitors.

the sum of quiescent power (PDQ) and additional

An optional supply decoupling capacitor across the

power dissipated in the output stage (PDL) to deliver

two power supplies (for bipolar operation) will

load power. Quiescent power is simply the specified

improve 2nd-harmonic distortion performance. Larger

no-load supply current times the total supply voltage

(2.2

µF to 6.8µF) decoupling capacitors, effective at

across the part. PDL depends on the required output

lower frequency, should also be used on the main

signal and load but, for a grounded resistive load, be

supply pins. These may be placed somewhat farther

at a maximum when the output is fixed at a voltage

from the device and may be shared among several

equal to 1/2 of either supply voltage (for equal

devices in the same area of the PCB.

bipolar supplies). Under this condition PDL = VS

2/(4

RL), where RL includes feedback network loading.

c) Careful selection and placement of external

components will preserve the high-frequency

Note that it is the power in the output stage and not

performance of the OPA875. Resistors should be a

the

load

that

determines

internal

power

very low reactance type. Surface-mount resistors

dissipation.

work

best

and

allow

tighter

overall

layout.

As a worst-case example, compute the maximum TJ

Metal-film and carbon composition, axially leaded

using an OPA875IDGK in the circuit of Figure 30

resistors can also provide good high-frequency

operating

the

maximum

specified

ambient

performance. Again, keep their leads and printed

temperature of +85

°C with its outputs driving a

circuit board (PCB) trace length as short as possible.

grounded 100

Ω load to +2.5V:

Never

use

wirewound

type

resistors

high-frequency

application.

Other

network

components, such as noninverting input termination

resistors, should also be placed close to the

package.

This worst-case condition does not exceed the

maximum

junction

temperature.

Normally,

this

d) Connections to other wideband devices on the

extreme case is not encountered. Careful attention to

board may be made with short direct traces or

internal power dissipation is required.

through onboard transmission lines. For short

connections, consider the trace and the input to the

next device as a lumped capacitive load. Relatively

wide traces (50mils to 100mils) should be used,

preferably with ground and power planes opened up

around them.

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