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UPD17P218 Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # UPD17P218
Description  MOS INTEGRATED CIRCUIT
PDF  32 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17P218 Datasheet(HTML) 14 Page - Renesas Technology Corp

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µPD17P218
12
3.
WRITING/VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
The program memory of the
µPD17P218 is a one-time PROM of 8192 x 16 bits. To write data to or verify this one-
time PROM, the pins shown in the following table are used. No address input pin is used, as the address is updated
by the clock input from the CLK pin.
Table 3-1 Pins Used to Write/Verify Program Memory
Pin Name
VPP
VDD
CLK
MD0-MD3
D0-D7
Function
Applies voltage when program memory is written/verified.
Apply +12.5 V to this pin.
Positive power supply.
Apply +6 V to write/verify program memory.
Input clock to update address when program memory is written/verified.
Program memory address is updated when four pulses are input to this pin.
Select operation mode when program memory is written/verified.
Input/output 8-bit data when program memory is written/verified.
3.1
OPERATION MODE FOR WRITING/VERIFICATION OF PROGRAM MEMORY
If +6 V is applied to the VDD and +12.5 V to the VPP pin after
µPD17P218 has been placed in the reset status for a
fixed time (VDD = 5V, RESET = 0V),
µPD17P218 enters program memory write/verify mode.
The MD0 to MD3 pins are used to set the operating modes listed in the following table.
Leave the pins not used for program memory writing/verification open or connect to GND through pull-down
resistors (470
Ω) (Refer to PIN CONFIGRATION (2) PROM programming mode).
Table 3-2 Operating Mode Specification
Operating Mode Specification
Remarks:
×: don‘t care (L or H)
MD0
MD1
MD2
MD3
HL
H
L
LH
H
H
LL
H
H
H
×
HH
VDD
+6 V
VPP
+12.5 V
Operating Mode
Program memory address 0 clear mode
Write mode
Verify mode
Program inhibit mode



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