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UPD17P218 Datasheet(PDF) 18 Page - Renesas Technology Corp |
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UPD17P218 Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 32 page ![]() µPD17P218 16 SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 5.5 V) Recommended Constants Oscillation frequency (fx) Note 1 1.0 4.0 8.0 MHz Oscillation stabilization 4ms time Note 2 Oscillation frequency (fx) Note 1 1.0 4.0 8.0 MHz Oscillation VDD = 4.5 to 5.5 V 10 ms stabilization time Note 2 30 ms Note 1: The oscillation frequency indicates only the characteristics of the oscillation circuit. 2: The oscillation stabilization time is the time required for oscillation to stabilize after VDD has been applied or the STOP mode has been released. Caution: Wire the shaded portion in the above figures as follows to prevent adverse influence of wiring capacitance when the system clock oscillation circuit is used: • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not place the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract a signal from the oscillation circuit. Ceramic Oscillator Crystal Oscillator After VDD has reached MIN value of oscillation voltage range Oscillator Item Conditions MIN. TYP. MAX. Unit 5 X IN X OUT X IN X OUT |
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