MP1660

– SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP86953 Rev. 1.0

www.MonolithicPower.com

10

6/9/2020

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© 2020 MPS. All Rights Reserved.

OPERATION

The MP1660 is a fully integrated, synchronous,

rectified, step-down, switch-mode converter.

Constant-on-time (COT) control is employed to

provide fast transient response and ease loop

stabilization. At the beginning of each cycle, the

high-side MOSFET (HS-FET) turns on when

the FB voltage (VFB) drops below the reference

voltage (VREF). The HS-FET turns on for a fixed

interval, determined by the one-shot on timer.

The on timer is determined by both the output

voltage and input voltage to keeps the switching

frequency fairly constant across the input

voltage range.

After the on period elapses, the HS-FET turns

off until the next period. By repeating this

operation, the converter regulates the output

voltage.

The device operates in continuous conduction

mode (CCM) when the output current is high

and the inductor current is always above 0A.

The low-side MOSFET (LS-FET) turns on when

the HS-FET is off to minimize conduction loss.

A dead short occurs between the input and

GND if both the HS-FET and LS-FET turn on at

the same time. This is called a shoot-through.

To

avoid

shoot-through,

a

dead

time

is

generated internally between the HS-FET off

and LS-FET on period, and vice versa.

If

the

MP1660

works

in

pulse-frequency

modulation

(PFM)

mode

during

light-load

operation, the device reduces the switching

frequency

automatically

to

maintain

high

efficiency, and the inductor current drops

almost to zero. If the inductor current reaches

zero, the low-side driver goes into tri-state (Hi-

Z). The output capacitors discharge slowly to

GND through R1 and R2. When VFB drops

below VREF, the HS-FET turns on. This greatly

improves device efficiency when the output

current is low.

Light-load operation is also called skip mode

because the HS-FET does not turn on as

frequently

as

it

does

under

heavy-load

conditions. The frequency at which the HS-FET

turns on is a function of the output current. As

the

output

current

increases,

the

current

modulator regulates over a shorter period, the

HS-FET turns on more frequently, and the

switching frequency increases in turn. The

output current (IOUT) reaches its critical level

when the current modulator time is zero. IOUT

can be calculated with Equation (1):

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2 L f

V





 



(1)

The device reverts to pulse-width modulation

(PWM) mode once the output current exceeds

the

critical

level.

Afterward,

the

switching

frequency remains fairly constant across the

output current range.

Enable (EN) Control

EN is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator; drive EN low to turn off the

regulator. An internal 1M

Ω resistor from EN to

GND allows EN to float, which shuts down the

IC.

EN is clamped internally using a 2.8V series

Zener diode (see Figure 2). Connecting the EN

input to VIN through a pull-up resistor limits the

EN input current below

100μA to prevent

damage to the Zener diode. For example, when

connecting a 100k

Ω pull-up resistor to 12V VIN,

IZENER = (12V - 2.8V) / (100kΩ + 35kΩ) = 68µA.

EN

Logic

1M

Ω

EN

GND

35k

Ω

2.8V

Figure 2: Zener Diode between EN and GND

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP1660 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 4.1V, while

its falling threshold is 3.7V.

Internal Soft Start (SS)

Soft start (SS) prevents the converter output

voltage

from

overshooting

during

start-up.

When the chip starts up, the internal circuitry

generates a soft-start voltage (VSS) that ramps

up from 0V to 1.2V. When VSS is below VREF,

VSS overrides VREF, so the error amplifier uses

VSS as the reference. When VSS exceeds VREF,

the error amplifier uses VREF as the reference.

The SS time is set to 1ms internally.