UPD17708 datasheet(306/358 Pages) RENESAS

306 / 358 page

304

µPD17704, 17705, 17707, 17708, 17709

20.6.3 Resetting device

The device can be reset (CE reset) by raising the CE pin.

The device can also be reset as follows:

•

Power-ON reset on application of supply voltage VDD

•

Watchdog timer reset for software hang-up detection and stack overflow/underflow reset

•

Reset by RESET pin

For details, refer to 21. RESET.

20.6.4 Signal input to CE pin

The CE pin does not accept a low level or high level of less than 167

µs to prevent malfunctioning due to noise.

The level of the signal input to the CE pin can be detected by the CE pin status detection flag of the CE pin interrupt

request register (RF address 3FH).

Figure 20-5 shows the relationship between the input signal and CE flag.

Figure 20-5. Relationship between Input Signal of CE Pin and CE Flag

CE pin

CE flag

Less than 167

167

PLL can operate

PLL disabled

PLL disabledNote

CE reset is effected in

synchronization with next

basic timer 0 carry FF

(When CE reset count

Less than 167

167

CE reset

Note

Unless the PLL mode selection register and PLL reference frequency selection register are rewritten by

software, the PLL disabled status is retained.

UPD17708 Datasheet(PDF) 306 Page - Renesas Technology Corp