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UPD17708 Datasheet(PDF) 309 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 309 Page - Renesas Technology Corp |
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309 / 358 page  307 µPD17704, 17705, 17707, 17708, 17709 21.2 CE Reset CE reset is effected by raising the CE pin. When the CE pin goes high, the next rising edge of the basic timer 0 carry FF setting pulse is counted. When the count value coincides with the value set to the CE reset timer carry counter register (1 to 15 counts), the reset signal is generated. When CE reset is effected, the program counter, stack, system registers, and some of the control registers are initialized to the initial values, and program execution is started from address 0000H. For the initial value of each register, refer to the description of each register. Figure 21-2. Configuration of CE Reset Timer Carry Counter Register Name Flag symbol b3 C E C N T 3 b2 C E C N T 2 b1 C E C N T 1 b0 C E C N T 0 Address 06H Read/Write R/W CE reset timer carry counter Power-ON reset WDT&SP reset CE reset Clock stop 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 Setting prohibited 1 count 2 counts 3 counts 4 counts 5 counts 6 counts 7 counts 8 counts 9 counts 10 counts 11 counts 12 counts 13 counts 14 counts 15 counts Sets number of counts of timer carry counter for CE reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Retained Retained |
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