UPD17708 datasheet(283/358 Pages) RENESAS

283 / 358 page

281

µPD17704, 17705, 17707, 17708, 17709

18.3.4 Function and operation of 16-bit counter

The 16-bit counter counts up the frequency input within selected gate time.

The 16-bit counter can be reset by writing “1” to the IFCRES flag of the IF counter control register.

Once the 16-bit counter has counted up to FFFFH, it remains at FFFFH until it is reset.

The following paragraphs (1) and (2) describe the operations when the IF counter function is selected and when

the external gate counter function is selected.

The value of the IF counter data register is read via data buffer.

Figure 18-8 shows the configuration and function of the IF counter data register.

(1) When IF counter is selected

The frequency input to the P1C0/FMIFC or P1C1/AMIFC pin is counted while the gate is open. Note, however,

that the frequency input to the P1C0/FMIFC is divided by two and counted.

The relationship between count value “x (decimal)” and input frequencies (fFMIFC and fAMIFC) is shown below.

• FMIFC

fFMIFC =

× 2 (kHz)

tGATE: gate time (1 ms, 4 ms, 8 ms)

tGATE

• AMIFC

fAMIFC =

(kHz)

tGATE: gate time (1 ms, 4 ms, 8 ms)

tGATE

(2) When external gate counter (FCG) is selected

The internal frequency is counted while the gate is opened by the signal input to the P2A1/FCG1 or P2A0/

FCG0 pin.

The relationship between the count value “x (decimal)” and the gate width tGATE of the input signal is shown

below.

tGATE =

(ms)

fr: internal frequency (1, 100, 900 kHz)

UPD17708 Datasheet(PDF) 283 Page - Renesas Technology Corp