UPD17708 datasheet(284/358 Pages) RENESAS

284 / 358 page

282

µPD17704, 17705, 17707, 17708, 17709

Figure 18-8. Configuration of IF Counter Data Register

Data buffer

DBF3

DBF2

Name

IF counter

data register

Symbol

IFC

Peripheral address

43H

DBF1

DBF0

b3 b2 b1 b0

b6 b5 b4

b10 b9 b8 b7

b13 b12

b15 b14

b11

Peripheral register

Transfer data

Valid data

GET can be executed

PUT changes nothing

Count value of frequency counter

216–1 (FFFFH)

IF counter function

• FMIF count mode of FMIFC pin

Counts rising edge of signal input to

P1C0/FMIFC pin via 1/2 divider

• AMIF count mode of AMIFC pin

Counts rising edge of signal input to

P1C1/AMIFC pin

• AMIF count mode of FMIFC pin

Counts rising edge of signal input to

P1C0/FMIFC pin

External gate counter function

Counts rising edge of internal reference

frequency signal from rising edge to next

rising edge of signal input to

P2A0/FCG0 or P2A1/FCG1 pin

Once the IF counter data register has counted up to FFFFH, it remains at FFFFH until the counter is reset.

UPD17708 Datasheet(PDF) 284 Page - Renesas Technology Corp

UPD17708 Datasheet(HTML) 284 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL