Analog Integrated Circuit Device Data

Freescale Semiconductor

17

33186

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum is provided as a supplement to the MC33186 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

Package and Thermal Considerations

The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-

specific environment. Stated values were obtained by measurement and

simulation according to the standards listed below.

20-PIN

HSOP-EP

33186DW

33186VW

DH SUFFIX

VW SUFFIX (Pb-FREE)

98ASH70273A

20-PIN HSOP-EP

Note For package dimensions, refer to

the 33186 data sheet.

=

.

P

Standards

Notes:

1.

Per JEDEC JESD51-2 at natural convection, still air condition.

2.

2s2p thermal test board per JEDEC JESD51-5 and

JESD51-7.

3.

Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

4.

Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.

Thermal resistance between the die junction and the exposed

pad surface; cold plate attached to the package bottom side,

remaining surfaces insulated.

Figure 28. Thermal Land Pattern for Direct Thermal

Attachment According to JESD51-5

Table 5. Thermal Performance Comparison

Thermal Resistance

[

°C/W]

(1), (2)

29

(2), (3)

9.0

(1), (4)

69

(5)

2.0

1.0

1.0

0.2

0.2

* All measurements

are in millimeters

Soldermast

openings

Thermal vias

connected to top

buried plane

20 Pin HSOP-EP

1.6 mm Pitch

16.0 mm x 11.0 mm Body

12.3 mm x 7.1 mm Exposed Pad