UPD178024 datasheet(41/58 Pages) RENESAS

41 / 58 page

µPD178023, 178024

Data Sheet U14126EJ2V0DS00

(2) Serial interface (TA = –40 to +85

°C, VDD = 3.5 to 5.5 V)

(a) Serial interface (IIC0)

I2C bus mode

Parameter

Symbol

Standard Mode

High-speed Mode

Unit

MIN.

MAX.

MIN.

MAX.

SCL0 clock frequency

fCLK

100

400

kHz

Bus free time (between stop and start

tBUF

4.7

–

1.3

–

µs

conditions)

Hold timeNote 1

tHD : STA

4.0

–

0.6

–

µs

SCL0 clock low-level width

tLOW

4.7

–

1.3

–

µs

SCL0 clock high-level width

tHIGH

4.0

–

0.6

–

µs

Start/restart condition setup time

tSU : STA

4.7

–

0.6

–

µs

Data hold

CBUS compatible master

tHD : DAT

5.0

–

µs

time

I2C bus

0Note 2

–0Note 2

0.9Note 3

µs

Data setup time

tSU : DAT

250

–

100Note 4

–ns

SDA0 and SCL0 signal rise time

–

1000

20+0.1CbNote 5

300

SDA0 and SCL0 signal fall time

–

300

20+0.1CbNote 5

300

Stop condition setup time

tSU : STO

4.0

–

0.6

–

µs

Pulse width of spike restrained by input filter

tSP

–

Each bus line capacitative load

–

400

–

400

Notes 1. The first clock pulse is generated at the start condition after this period.

2. The device needs to internally supply a hold time of at least 300 ns for the SDA0 signal to fill the

undefined area at the falling edge of the SCL0 (VIHmin. of the SCL0 signal).

3. Unless the device extends the low hold time (tLOW) of the SCL0 signal, it is necessary to fill only the

maximum data hold time (tHD : DAT).

4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy

the following conditions:

• When the device does not extend the low hold time of the SCL0 signal

tSU : DAT

≥ 250 ns

• When the device extends the low hold time of the SCL0 signal

Send the next data bit to the SDA line before releasing the SCL0 line (tRmax. + tSU:DAT = 1000 + 250

= 1250 ns : in the standard mode I2C bus specification)

5. Cb: Total capacitance of one bus line (unit: pF)

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