UPD178024 datasheet(6/58 Pages) RENESAS

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µPD178023, 178024

Data Sheet U14126EJ2V0DS00

FUNCTIONAL OUTLINE

(1/2)

Item

µPD178023

µPD178024

Internal

ROM

24 Kbytes

32 Kbytes

memory

(Mask ROM)

High-speed RAM

1024 bytes

General-purpose register

8 bits

× 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.45

µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of fX = 4.5 MHz)

Instruction set

• 16-bit operation

• Multiplication/division (8 bits

× 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Total

: 62 pins

• CMOS I/O

: 53 pins

• CMOS input

: 6 pins

• N-ch open-drain output : 3 pins

A/D converter

8-bit resolution

× 6 channels (VDD = 3.5 to 5.5 V)

Serial interface

• I2C bus modeNote : 1 channel

• 3-wire mode

: 1 channel

• UART mode

: 1 channel

Timer

• Basic timer (timer carry FF (10 Hz)) : 1 channel

• 8-bit timer/event counter

: 2 channels

• Watchdog timer

: 1 channel

Buzzer output

1 channel (1 kHz, 1.5 kHz, 3 kHz, 4 kHz)

Vectored

Maskable

Internal : 11

interrupt

External: 5

source

Non-maskable

Internal: 1

Software

PLL

Division mode

2 types

frequency

• Direct division mode (VCOL pin)

synthesizer

• Pulse swallow mode (VCOL and VCOH pins)

Reference frequency

Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)

Charge pump

Error out output: 2 pins

Phase comparator

Unlock detectable in software

Note

When the I2C bus mode is used (including when the mode is implemented in software without using the

peripheral hardware), consult NEC when ordering a mask.

UPD178024 Datasheet(PDF) 6 Page - Renesas Technology Corp

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