 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD178024 Datasheet(PDF) 27 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD178024 Datasheet(HTML) 27 Page - Renesas Technology Corp |
|
|
27 / 58 page  25 µPD178023, 178024 Data Sheet U14126EJ2V0DS00 Figure 3-9. Block Diagram of Serial Interface SIO3 Figure 3-10. Block Diagram of Serial Interface UART0 Internal bus 8 Interrupt request signal generation circuit Selector Serial clock counter Serial clock control circuit Serial I/O shift registe 3 (SIO3) SI3/P70 SO3/P71 P71 output latch PM71 PM72 SCK3/P72 INTCSI3 fX/2 4 fX/2 5 fX/2 6 P72 output latch Internal bus Receive buffer register 0 (RXB0) RXD0/P74 TXD0/P75 P75 output latch PM75 Receive shift register 0 (RX0) PE0 FE0 OVE0 Reception control circuit (parity check) Transmit shift register 0 (TXS0) Transmission control circuit (parity append) INTSER0 INTST0 Baud rate generator fX/2-fX/28 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 0 INTSR0 Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
