IMX8ULPCEC datasheet(23/105 Pages) NXP

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• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

• Low Power Inter-Integrated Circuit (LPI2C)

• Low Power Serial Peripheral Interface (LPSPI)

• Rapid General-Purpose Input and Output with 2 Ports (RGPIO2P)

• Flexible Input/Output (FlexIO)

• Flexible Controlled Area Network (FlexCAN)

See the i.MX 8ULP modules list for more details.

3 System control modules

3.1 JTAG—system control

Joint Test Action Group Controller (JTAGC) provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE

1149.1-2001 standard.

3.2 JTAG device identification register

The device identification register (Device_ID) is 32-bit length register which provides component identification information. For

more details, see the device identification register section of i.MX 8ULP Applications Processor Reference Manual for details. This

table shows the Device_ID fields for each i.MX 8ULP silicon revision.

Table 4. JTAG device identification register information

Silicon Revision

Version (4 MSBs)

Part Number

Manufacturer Identity

IEEE 1149.1

Requirement (LSB)

0001

1000100011101000

00000001110

The contents of the Device_ID register are also mirrored in a SIM register called MIRROR_OF_JTAG_ID_REG

(address:2802_A010). See the i.MX8ULPRM for details.

3.3 Oscillators and PLLs

3.3.1 System oscillator (SYS OSC)

The system oscillator (SYS OSC) is a crystal oscillator. The SYS OSC, in conjunction with an external crystal or resonator,

generates a reference clock for this chip. It also provides the option for external input bypass clock from the EXTAL signal directly.

3.3.2 Real-Time Clock Oscillator (RTC OSC)

The RTC OSC module provides the clock source for the Real-Time Clock module. The RTC OSC module, in conjunction with an

external crystal, generates a 32.768 kHz reference clock for the RTC.

3.3.3 192 MHz Free-Running Oscillator (FRO)

Low Power internal reference clock (IRC) with tuning logic to generate 192 MHz. System defaults to FRO for as initial boot clock.

NXP Semiconductors

System control modules

i.MX 8ULP Applications Processor—Commercial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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