IMX8ULPCEC datasheet(60/105 Pages) NXP

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5.4.4.1 Ethernet Controller (ENET) AC electrical specifications

The following timing specifications are defined at the chip I/O pin and must be translated appropriately to arrive at timing

specifications/constraints for the physical interface.

5.4.4.1.1 ENET MII mode timing

5.4.4.1.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER, and

ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum

frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency.

The following table describes MII receive signal timings and the figure below depicts the timing parameters (M1–M4).

Table 38. MII receive signal timing

Characteristic

Min.

Max.

Unit

ENET_RX_DATA3,2,1,0,

ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

ENET_RX_CLK to

ENET_RX_DATA3,2,1,0,

ENET_RX_EN, ENET_RX_ER hold

ENET_RX_CLK pulse width high

35%

65%

ENET_RX_CLK period

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0

ENET_RX_ER

ENET_RX_EN

(inputs)

Figure 17. MII receive signal timing diagram

5.4.4.1.1.2 MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and

ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum

frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency.

The table below describes the timing parameters (M5–M8).

NXP Semiconductors

Specifications—application domain

i.MX 8ULP Applications Processor—Commercial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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