ATMEGA162 datasheet(45/325 Pages) ATMEL

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ATmega162/V

2513I–AVR–02/07

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,

Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-

flow o r Ou tput Comp are event from T im e r/Coun ter2 if the corre sp ond ing

Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable

bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec-

ommended instead of Power-save mode because the contents of the registers in the

Asynchronous Timer should be considered undefined after wake-up in Power-save

mode if AS2 is 0.

This sleep mode basically halts all clocks except clk

ASY, allowing operation only of asyn-

chronous modules, including Timer/Counter 2 if clocked asynchronously.

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the main Oscillator is kept running. From Standby

mode, the device wakes up in six clock cycles.

Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is

identical to Power-save mode with the exception that the main Oscillator is kept running.

From Extended Standby mode, the device wakes up in six clock cycles.

Notes:

1. External Crystal or resonator selected as clock source

2. If AS

2 bit in ASSR is set

3. For INT1 and INT0, only level interrupt

Table 17. Active Clock domains and Wake up sources in the different sleep modes

Active Clock domains

Oscillators

Wake-up Sources

Sleep Mode

clk

CPU

clk

FLASH

clk

ASY

Main Clock

Source Enabled

Timer Osc

Enabled

INT2

INT1

INT0

and Pin Change

Timer

SPM/

EEPROM

Ready

Other

I/O

Idle

X(2)

Power-down

X(3)

Power-save

X(2)

X(3)

X(2)

Standby(1)

XX(3)

Extended Standby(1)

X(2)

XX(2)

X(3)

X(2)

ATMEGA162 Datasheet(PDF) 45 Page - ATMEL Corporation

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