ATMEGA649 datasheet(121/375 Pages) ATMEL

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ATmega329/3290/649/6490

2552H–AVR–11/06

OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In phase correct PWM mode the counter is incremented until the counter value matches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the

value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter

has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM

mode is shown on Figure 48. The figure shows phase correct PWM mode when OCR1A

or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a

histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-

sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be

set when a compare match occurs.

Figure 48. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-

TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or

ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are

updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-

erate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are

masked to zero when any of the OCR1x Registers are written. As the third period shown

in Figure 48 illustrates, changing the TOP actively while the Timer/Counter is running in

the phase correct mode can result in an unsymmetrical output. The reason for this can

be found in the time of update of the OCR1x Register. Since the OCR1x update occurs

at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-

PCPWM

TOP

()

log

()

log

-----------------------------------

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

ATMEGA649 Datasheet(PDF) 121 Page - ATMEL Corporation

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