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ATMEGA649 Datasheet(PDF) 161 Page - ATMEL Corporation |
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ATMEGA649 Datasheet(HTML) 161 Page - ATMEL Corporation |
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161 / 375 page ![]() 161 ATmega329/3290/649/6490 2552H–AVR–11/06 USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART Transmitter is shown in Figure 70. CPU acces- sible I/O Registers and I/O pins are shown in bold. The Power Reduction USART bit, PRUSART0, in “PRR – Power Reduction Register” on page 38 must be written to zero to enable USART0 module. Figure 70. USART Block Diagram (1) Note: 1. Refer to Figure 1 on page 2, Figure 2 on page 3, “Alternate Functions of Port E” on page 75 for USART pin placement. PARITY GENERATOR UBRR[H:L] UDR (Transmit) UCSRA UCSRB UCSRC BAUD RATE GENERATOR TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER RxD TxD PIN CONTROL UDR (Receive) PIN CONTROL XCK DATA RECOVERY CLOCK RECOVERY PIN CONTROL TX CONTROL RX CONTROL PARITY CHECKER OSC SYNC LOGIC Clock Generator Transmitter Receiver |
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