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OPA392DBVT Datasheet(PDF) 22 Page - Texas Instruments

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Part # OPA392DBVT
Description  OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim™ Operational Amplifiers
PDF  41 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OPA392DBVT Datasheet(HTML) 22 Page - Texas Instruments

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9.3 Power Supply Recommendations
The OPAx392 are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V).
CAUTION
Exceeding supply voltages listed in the Absolute Maximum Ratings table can permanently damage
the device.
9.4 Layout
9.4.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short, and when possible, use a printed-circuit board
(PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place
a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout the analog
circuit to improve performance and provide benefits such as reducing the electromagnetic interference (EMI)
susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by making
sure these potentials are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Use guard traces to minimize leakage current when ultra-low bias current is required.
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
9.4.2 Layout Example
+
V
IN
V
OUT
R
G
R
F
Figure 9-3. OPA392 Layout Schematic
CBYPASS
Minimize
parasitic
inductance by
placing bypass
capacitor close
to V+.
RF
Route trace under package for output to
feedback resistor connection.
V+
±IN
+IN
V±
OUT
Keep high
impedance
input signal
away from
noisy traces.
VIN
VOUT
VS
RG
Figure 9-4. OPA392 Layout Example
OPA392, OPA2392
SBOS926E – JANUARY 2021 – REVISED SEPTEMBER 2023
www.ti.com
22
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: OPA392 OPA2392



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