TDA8844 datasheet(13/68 Pages) PHILIPS

13 / 68 page

December 16, 1997

Philips Semiconductors

Tentative Device Speciﬁcation

I2C-bus controlled PAL/NTSC/SECAM TV

processors

TDA884X/5X-N2 series

Video switches

The circuits have two CVBS inputs (internal and external

CVBS) and a Y/C input. When the Y/C input is not required

the Y input can be used as third CVBS input. The switch

configuration is given in Fig.6. The selection of the various

sources is made via the I2C-bus.

For the TDA 884X devices the video switch configuration

is identical to the switch of the TDA 8374/75 series. So the

circuit has one CVBS output (amplitude of 2 VP-P for the

TDA 884X series) and the I2C-bus control is similar to that

of the TDA 8374/75. For the TDA 885X IC’s the video

switch circuit has a second output (amplitude of 1 VP-P)

which can be set independently of the position of the first

output. The input signal for the decoder is also available on

the CVBS1-output.

Therefore this signal can be used to drive the Teletext

decoder. If S-VHS is selected for one of the outputs the

luminance and chrominance signals are added so that a

CVBS signal is obtained again.

Sound circuit

The sound bandpass and trap filters have to be connected

externally. The filtered intercarrier signal is fed to a limiter

circuit and is demodulated by means of a PLL

demodulator. This PLL circuit tunes itself automatically to

the incoming carrier signal so that no adjustment is

required.

The volume is controlled via the I2C-bus. The deemphasis

capacitor has to be connected externally. The

non-controlled audio signal can be obtained from this pin

(via a buffer stage).

The FM demodulator can be muted via the I2C-bus. This

function can be used to switch-off the sound during a

channel change so that high output peaks are prevented.

The TDA 8840/41/42/46 contain an Automatic Volume

Levelling (AVL) circuit which automatically stabilises the

audio output signal to a certain level which can be set by

the viewer by means of the volume control. This function

prevents big audio output fluctuations due to variations of

the modulation depth of the transmitter. The AVL function

can be activated via the I2C-bus.

Synchronisation circuit

The sync separator is preceded by a controlled amplifier

which adjusts the sync pulse amplitude to a fixed level.

These pulses are fed to the slicing stage which is operating

at 50% of the amplitude. The separated sync pulses are

fed to the first phase detector and to the coincidence

detector. This coincidence detector is used to detect

whether the line oscillator is synchronised and can also be

used for transmitter identification. This circuit can be made

less sensitive by means of the STM bit. This mode can be

used during search tuning to avoid that the tuning system

will stop at very weak input signals. The first PLL has a

very high statical steepness so that the phase of the

picture is independent of the line frequency.

The horizontal output signal is generated by means of an

oscillator which is running at twice the line frequency. Its

frequency is divided by 2 to lock the first control loop to the

incoming signal. The time-constant of the loop can be

forced by the I2C-bus (fast or slow). If required the IC can

select the time-constant depending on the noise content of

the incoming video signal.

The free-running frequency of the oscillator is determined

by a digital control circuit which is locked to the reference

signal of the colour decoder. When the IC is switched-on

the horizontal output signal is suppressed and the

oscillator is calibrated as soon as all sub-address bytes

have been sent. When the frequency of the oscillator is

correct the horizontal drive signal is switched-on. To obtain

a smooth switching-on and switching-off behaviour of the

horizontal output stage the horizontal output frequency is

doubled during switch-on and switch-off (slow start/stop).

During that time the duty cycle of the output pulse has such

a value that maximum safety is obtained for the output

stage.

To protect the horizontal output transistor the horizontal

drive is immediately switched off when a power-on-reset is

detected. The drive signal is switched-on again when the

normal switch-on procedure is followed, i.e. all

sub-address bytes must be sent and after calibration the

horizontal drive signal will be released again via the slow

start procedure. When the coincidence detector indicates

an out-of-lock situation the calibration procedure is

repeated. The circuit has a second control loop to generate

the drive pulses for the horizontal driver stage. The

horizontal output is gated with the flyback pulse so that the

horizontal output transistor cannot be switched-on during

the flyback time.

Via the I2C-bus adjustments can be made of the horizontal

and vertical geometry. The vertical sawtooth generator

drives the vertical output drive circuit which has a

differential output current. For the E-W drive a single

ended current output is available. A special feature is the

zoom function for both the horizontal and vertical

deflection and the vertical scroll function which are

available in some versions. When the horizontal scan is

reduced to display 4:3 pictures on a 16:9 picture tube an

accurate video blanking can be switched on to obtain well

defined edges on the screen.

TDA8844 Datasheet(PDF) 13 Page - NXP Semiconductors

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