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TDA8844 Datasheet(PDF) 23 Page - NXP Semiconductors |
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TDA8844 Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 68 page ![]() December 16, 1997 23 Philips Semiconductors Tentative Device Specification I2C-bus controlled PAL/NTSC/SECAM TV processors TDA884X/5X-N2 series Table 50 Bypass of chroma base-band delay line Table 51 Automatic colour limiting Table 52 Enable external comb filter Table 53 Start-up mode of black current loop; note 1 Note 1. When the circuit is in the automatic mode the RGB drive is switched-on as soon as the black current loop has stabilised. Under control of the µ-processor the condition of the black current loop is indicated via the BCF bit. When this bit changes to 0 the RGB drive can be switched-on by setting the AST bit to 0. BPS DELAY LINE MODE 0 active 1 bypassed ACL COLOUR LIMITING 0 not active 1 active CMB COMB FILTER 0 disabled 1 enabled AST MODE 0 automatic mode; 1 switch-on under control of µ-processor Table 54 Cathode drive level Note 1. The given values are valid for the following conditions: - Nominal CVBS input signal - Settings for contrast, WPA and peaking nominal - Black- and blue-stretch switched-off - Gain of output stage such that no clipping occurs - Beam current limiting not active The tolerance on these values is about ± 3 V. Table 55 Y-delay adjustment; note 1 Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. This is only valid for a CVBS signal without group delay distortions. Table 56 Dynamic skin control on/off Table 57 Dynamic skin control angle CL2 CL1 CL0 SETTING CATHODE DRIVE AMPLITUDE; NOTE 1 000 57VBL-WH 0 0 1 63 VBL-WH 0 1 0 70 VBL-WH 0 1 1 77 VBL-WH 1 0 0 84 VBL-WH 1 0 1 91 VBL-WH 1 1 0 99 VBL-WH 1 1 1 107 VBL-WH YD0 to YD3 Y-DELAY YD3 YD3 ∗ 160 ns + YD2 YD2 ∗ 80 ns + YD1 YD1 ∗ 40 ns + YD0 YD0 ∗ 40 ns DS MODE 0off 1on DSA ANGLE OF CORRECTION 0 correction angle 123 degrees 1 correction angle 117 degrees |
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