TDA8844 datasheet(16/68 Pages) PHILIPS

16 / 68 page

December 16, 1997

Philips Semiconductors

Tentative Device Speciﬁcation

I2C-bus controlled PAL/NTSC/SECAM TV

processors

TDA884X/5X-N2 series

An important property of the 2-point stabilisation is that the

off-set as well as the gain of the RGB path is adjusted by

the feedback loop. Hence the maximum drive voltage for

the cathode is fixed by the relation between the test

pulses, the reference current and the relative gain setting

of the 3 channels. This has the consequence that the drive

level of the CRT cannot be adjusted by adapting the gain

of the RGB output stage. Because different picture tubes

may require different drive levels the typical “cathode drive

level” amplitude can be adjusted by means of an I2C-bus

setting. Dependent on the chosen cathode drive level the

typical gain of the RGB output stages can be fixed taking

into account the drive capability of the RGB outputs (pins

19 to 21). More details about the design will be given in the

application report.

The measurement of the “high” and the “low” current of the

2- point stabilisation circuit is carried out in 2 consecutive

fields. The leakage current is measured in each field. The

maximum allowable leakage current is 100

µA

When the TV receiver is switched-on the RGB output

signals are blanked and the black current loop will try to set

the right picture tube bias levels. Via the AST bit a choice

can be made between automatic start-up or a start-up via

the

µ-processor. In the automatic mode the RGB drive

signals are switched-on as soon as the black current loop

has been stabilised. In the other mode the BCF bit is set to

0 when the loop is stabilised. The RGB drive can than be

switched-on by setting the AST bit to 0. In the latter mode

some delay can be introduced between the setting of the

BCF bit and the switching of the AST bit so that switch-on

effects can be suppressed.

It is also possible to start-up the devices with a fixed

internal delay (as with the TDA 837X and the TDA884X/5X

N1). This mode is activated with the BCO bit.

The vertical blanking is adapted to the incoming CVBS

signal (50 Hz or 60 Hz). When the flyback time of the

vertical output stage is longer than the 60 Hz blanking time

the blanking can be increased to the same value as that of

the 50 Hz blanking. This can be set by means of the LBM

bit.

For an easy (manual) adjustment of the Vg2 control voltage

the VSD bit is available. When this bit is activated the black

current loop is switched-off, a fixed black level is inserted

at the RGB outputs and the vertical scan is switched-off so

that a horizontal line is displayed on the screen. This line

can be used as indicator for the Vg2 adjustment. Because

of the different requirements for the optimum cut-off

voltage of the picture tube the RGB output level is

adjustable when the VSD bit is activated. The control

range is 2.5

± 0.7 V and can be controlled via the

brightness control DAC.

It is possible to insert a so called “blue back” back-ground

level when no video is available. This feature can be

activated via the BB bit in the control2 subaddress.

I2C-BUS SPECIFICATION

The slave address of the IC’s is given in Fig.7. The circuit

operates up to clock frequencies of 400 kHz.

Start-up procedure

Read the status bytes until POR = 0 and send all

subaddress bytes. The horizontal output signal is

switched-on when the oscillator is calibrated.

Each time before the data in the IC is refreshed, the status

bytes must be read. If POR = 1, the procedure mentioned

above must be carried out to restart the IC.

When this procedure is not followed the horizontal

frequency may be incorrect after power-up or after a

power dip.

handbook, halfpage

MLA743

101

1/0

R/W

Fig.7 Slave address (8A).

TDA8844 Datasheet(PDF) 16 Page - NXP Semiconductors

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