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CDC706 Datasheet(PDF) 20 Page - Texas Instruments

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Part # CDC706
Description  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
PDF  41 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDC706 Datasheet(HTML) 20 Page - Texas Instruments

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CDC706
SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
Byte 25, Bit [6:4]: SSC Modulation Amount (1)
SSC2
SSC1
SSC0
Function
Default(2)
0
0
0
SSC Modulation Amount 0% = SSC bypass for PLL(3)
Yes
0
0
1
SSC Modulation Amount
±0.1% (center spread)
0
1
0
SSC Modulation Amount
±0.25% (center spread)
0
1
1
SSC Modulation Amount
±0.4% (center spread)
1
0
0
SSC Modulation Amount 1% (down spread)
1
0
1
SSC Modulation Amount 1.5% (down spread)
1
1
0
SSC Modulation Amount 2% (down spread)
1
1
1
SSC Modulation Amount 3% (down spread)
(1)
The PLL has to be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by following
programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Amount (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).
(2)
Unless customer specific setting.
(3)
If SSC bypass is selected, SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of
PLL2 is not affected by this mode and can still be used.
Byte 26, Bit [6:0]: Byte Count(1)
BC6
BC5
BC4
BC3
BC2
BC1
BC0
No. of Bytes
Default(2)
0
0
0
0
0
0
0
Not allowed
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
•
•
•
0
0
1
1
0
1
1
27
Yes
•
•
•
1
1
1
1
1
0
1
125
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
(1)
Defines the number of Bytes, which will be sent from this device at the next Block Read protocol.
(2)
Unless customer specific setting.
20
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