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Spread Spectrum Clocking and EMI Reduction

Down Spread 3%

11.3dB

7dB

Center Spread + 0.4%

Down Spread 3%

11.3dB

11.3 dB

7dB

7 dB

Center Spread + 0.4%

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Additionally, each PLL supports two bypass options:

• PLL Bypass and

• VCO Bypass

In PLL bypass mode, the PLL completely is bypassed, so that the input clock is switched directly to the

Output-Switch-A (SWAPxx of Byte 9 to 12). In the VCO bypass mode, only the VCO of the respective PLL is

bypassed by setting PLLxMUX to 1 (Bit [7:5] of Byte 3). But the divider M still is useable and expands the output

divider by additional 9-bits. This gives a total divider range of M x P = 511 x 127 = 64897. In VCO bypass mode

the respective PLL block is powered down and minimizes current consumption.

Table 3. Example for Divide, Multiplication, and Bypass Operation

Divider

Function

[MHz]

[MHz]

[MHz]

M

N

P

N/M

30.72

155.52

155.52

16

81

1

5.0625

155.52

27

270

270

1

10

1

10

270

VCO bypass

30.72

0.06

0.06

8

—

64

—

—

(1)

P-divider of Output-Switch-Matrix is included in the calculation.

(2)

(3)

In addition to the basic PLL function, PLL2 supports spread spectrum clocking (SSC) as well. Thus, PLL 2

features two outputs, a SSC output and a non-SSC output. Both outputs can be used in parallel. The mean

phase of the Center Spread SSC modulated signal is equal to the phase of the non-modulated input frequency.

SSC is selected by Output-Switch-A (SWAPxx of Byte 9 to 12).

SSC also is bypass-able (Byte 25, Bit [6:4]), which powers-down the SSC output and set it to logic low state.

The non-SSC output of PLL2 is not affected by this mode and can still be used.

SSC is an effective method to reduce electro-magnetic interference (EMI) noise in high-speed applications. It

reduces the RF energy peak of the clock signal by modulating the frequency and spread the energy of the signal

to a broader frequency range. Because the energy of the clock signal remains constant, a varying frequency that

broadens the overtones necessarily lowers their amplitudes. Figure 19 shows the effect of SSC on a 54-MHz

clock signal for DSP

Figure 19. Spread Spectrum Clocking With Center Spread and Down Spread

The peak amplitude of the modulated clock is 11.3 dB lower than the non-modulated carrier frequency for down

spread and radiated less electro-magnetic energy.

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