CDC706 datasheet(31/41 Pages) TI

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CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Phase jitter (t

jit(phase)) is the long-term variation of the clock signal. It is the cumulative deviation in t(Θ) for a

controlled edge with respect to a t(

Θ) mean in a random sample of cycles. Phase jitter, Time Interval Error (TIE),

or Wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is

defined as phase variation at rates less than 10 Hz while jitter is defined as phase variation greater than 10 Hz.

The measurement interval must be long enough to gain a meaningful result. Wander can be caused by

temperature drift, aging, supply voltage drift, etc.

Figure 28. Snapshot of Phase Jitter

Jitter depends on the VCO frequency (fVCO) of the PLL. A higher fVCO results in better jitter performance

compared to a lower fVCO. The VCO frequency can be defined via the M- and N-divider of the PLL

As the CDC706 supports a pretty wide frequency range, the device offers a VCO Frequency Selection Bit, Bit

[7:5] of Byte 6. This bit defines the jitter-optimized frequency range of each PLL. The user can select between

the normal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure 29

shows the jitter performance over fVCO for the two frequency ranges.

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CDC706 Datasheet(PDF) 31 Page - Texas Instruments