TMD26353M datasheet(11/48 Pages) OSRAM

11 / 48 page

Page 10

Datasheet, Public

Document Feedback

[v2-00] 2023-Jan-04

TMD2635 − Detailed Description

Figure 11:

I²C Schemes

Figure 12:

I²C Address Selection

I²C Write Transaction

A write transaction consists of a START, CHIP-ADDRESSWRITE,

byte (9TH clock pulse) the slave places an ACKNOWLEDGE/

NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is

transmitted by the slave, the master may issue a STOP.

I²C Read Transaction

A Read transaction consists of a START, CHIP-ADDRESSWRITE,

and STOP. Following all but the final byte the master places an

ACK on the bus (9TH clock pulse). Termination of the Read

transaction is indicated by a NACK being placed on the bus by

the master, followed by STOP.

Alternately, if the previous I²C transaction was a read, the

internal register address buffer is still valid, allowing the

transaction to proceed without “re”-specifying the register

address. In this case the transaction consists of a START,

CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but

Master I²C Bus Signal

Clock

Data

7-Bit I²C Address

SCL

SDA

0x39

SDA

SCL

0x38

SCL

SDA

TMD2635

(0x39)

SCL

SDA

TMD2635

(0x38)

clock

data

TMD26353M Datasheet(PDF) 11 Page - OSRAM GmbH

TMD26353M Datasheet(HTML) 11 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL