56F8322 datasheet(125/136 Pages) FREESCALE

125 / 136 page

Power Consumption

56F8322 Technical Data, Rev. 16

Freescale Semiconductor

125

Preliminary

C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the

56800E core and standard cell logic.

D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading

on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two

of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero

Y-intercept.

Note: VREFH is tied to VDDA and VREFLO is tied to VSSA inside this package.

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and

frequency at which the outputs change. Table 10-25 provides coefficients for calculating power dissipated

in the IO cells as a function of capacitive load. In these cases:

TotalPower =

Σ((Intercept + Slope*Cload)*frequency/10MHz)

where:

•

Summation is performed over all output pins with capacitive loads

•

TotalPower is expressed in mW

•

Cload is expressed in pF

Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found

to be fairly low when averaged over a period of time.

E, the external [static component], reflects the effects of placing resistive loads on the outputs of the

device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V =

0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs

driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.

In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,

as it is assumed to be negligible.

Table 10-25 IO Loading Coefficients at 10MHz

Intercept

Slope

PDU08DGZ_ME

1.3

0.11mW / pF

PDU04DGZ_ME

1.15mW

0.11mW / pF

56F8322 Datasheet(PDF) 125 Page - Freescale Semiconductor, Inc