ADP3192A datasheet(22/32 Pages) AD

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ADP3192A

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The two resistors RLL1 and RLL2 set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into

the LLSET pin to set the load line slope RO of the VR according

to the following equation:

CSA

(14)

The resistor values for RLL1 and RLL2 are limited by two factors.

•

The minimum value is based upon the loading of the

CSCOMP pin. This pin’s drive capability is 500 μA, and the

majority of this should be allocated to the CSA feedback. If

the current through RLL1 and RLL2 is limited to 10% of this

drive capability (50 μA), the following limit can be placed

on the minimum value for RLL1 and RLL2:

−

≥

CSA

LIM

(15)

Here, ILIM is the current-limit current, which is the

maximum signal level that the CSA responds to.

•

The maximum value is based upon minimizing induced

dc offset errors based on the bias current of the LLSET pin.

To keep the induced dc error less than 1 mV, which makes

this error statistically negligible, place the following limit

on the parallel combination of RLL1 and RLL2:

120

−

≤

= 8.33 kΩ

(16)

Select minimum value resistors to reduce the noise and parasitic

susceptibility of the feedback path.

By combining Equation 16 with Equation 14 and selecting

minimum values for the resistors, the following equations result:

LIM

(17)

CSA

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

(18)

Therefore, both RLL1 and RLL2 need to be in parallel and less than

8.33 kΩ.

Another useful feature for some VR applications is the ability to

select different load lines. Figure 12 shows an optional MOSFET

switch that allows this feature. Here, design for RCSA = RO(MAX)

(selected with QLL on), and then use Equation 14 to set RO = RO(MIN)

(selected with QLL off).

For this design, RCSA = RO = 1 mΩ. As a result, connect LLSET

directly to CSCOMP; the RLL1 and RLL2 resistors are not needed.

OUTPUT OFFSET

The Intel specification requires that at no load, the nominal output

voltage of the regulator be offset to a value lower than the nominal

voltage corresponding to the VID code. The offset is set by a

constant current source flowing out of the FB pin (IFB) and flowing

through RB. The value of RB can be found using Equation 19.

ONL

VID

−

μA

285

−

(19)

The closest standard 1% resistor value is 1.00 kΩ.

COUT SELECTION

The required output decoupling for the regulator is typically

recommended by Intel for various processors and platforms.

Use some simple design guidelines to determine the require-

ments. These guidelines are based on having both bulk

capacitors and ceramic capacitors in the system.

First, select the total amount of ceramic capacitance. This is

based on the number and type of capacitor to be used. The best

location for ceramic capacitors is inside the socket with 12 to 18,

1206 size being the physical limit. Other capacitors can be

placed along the outer edge of the socket as well.

To determine the minimum amount of ceramic capacitance

required, start with a worst-case load step occurring right after

a switching cycle stops. The ceramic capacitance then delivers

the charge to the load while the load is ramping up and until the

VR has responded with the next switching cycle.

Equation 20 gives the designer a rough approximation for

determining the minimum ceramic capacitance. Due to the

complexity of the PCB parasitics and bulk capacitors, the actual

amount of ceramic capacitance required can vary.

()

⎥

⎦

⎤

⎢

⎣

⎡

−

⎟

⎠

⎞

⎜

⎝

⎛ −

≥

MIN

(20)

The typical ceramic capacitors consist of multiple 10 μF or 22 μF

capacitors. For this example, Equation 20 yields 180.8 μF, therefore,

18, 10 μF ceramic capacitors suffice.

Next, an upper limit is imposed on the total amount of bulk

capacitance (CX) when the user considers the VID on-the-fly

voltage stepping of the output (voltage step VV in time tV with

error of VERR).

A lower limit is based on meeting the capacitance for load

release for a given maximum load step (ΔIO) and a maximum

allowable overshoot. The total amount of load release voltage

is given as ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum

allowable overshoot voltage.

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