ADP3192A datasheet(25/32 Pages) AD

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ADP3192A

Rev. 0 | Page 25 of 32

COMP PIN RAMP

For the ADP3192A, the maximum COMP voltage (VCOMP(MAX))

is 4.0 V, and the COMP pin bias voltage (VBIAS) is 1.1 V. In

this example, the maximum duty cycle is 0.61 and the peak

current is 62 A.

A ramp signal on the COMP pin is due to the droop voltage

and output voltage ramps. This ramp amplitude adds to the

internal ramp to produce the following overall ramp signal

at the PWM input:

()

⎟

⎠

⎞

⎜

⎝

⎛

−

(30)

The limit of the peak per-phase current described earlier during

the secondary current limit is determined by

()

MAX

BIAS

CLAMPED

COMP

PHLIM

−

≅

(34)

For the ADP3192A, the current balancing amplifier gain (AD) is

5 and the clamped COMP pin voltage is 2 V. Using an RDS(MAX)

of 2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached only

with an absolute short at the output and only if the current-limit

latch-off function shuts down the regulator before overheating

can occur.

In this example, the overall ramp signal is 0.46 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to be at least 0.5 V by decreasing the ramp resistor for noise

immunity. Because there is only 0.46 V initially, a ramp resistor

value of 332 kΩ is chosen for this example, yielding an overall

ramp of 0.51 V.

CURRENT-LIMIT SETPOINT

FEEDBACK LOOP COMPENSATION DESIGN

To select the current-limit setpoint, first find the resistor value

for RLIM. The current-limit threshold for the ADP3192A is set

with a constant current source flowing out of the ILIMIT pin,

which sets up a voltage (VLIM) across RLIM with a gain of

82.6 mV/V (ALIM). Thus, increasing RLIM now increases the

current limit. RLIM can be found using

Optimized compensation of the ADP3192A allows the best

possible response of the regulator output to a load change.

REF

CSA

LIM

ILIMIT

LIM

(31)

The basis for determining the optimum compensation is to

make the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop

resistance (RO). With the resistive output impedance, the output

voltage droops in proportion to the load current at any load

current slew rate. This ensures optimal positioning and

minimizes the output decoupling.

Here, ILIM is the peak average current limit for the supply output.

The peak average current is the dc current limit plus the output

ripple current. In this example, choosing a dc current limit of

159 A and having a ripple current of 11 A gives an ILIM of 170 A.

This results in an RLIM = 205.8 kΩ, for which 205 kΩ is chosen

as the nearest 1% value.

Because of the multimode feedback structure of the ADP3192A,

the feedback compensation must be set to make the converter

output impedance work in parallel with the output decoupling

to make the load look entirely resistive. Compensation is

needed for several poles and zeros created by the output

inductor and the decoupling capacitors (output filter).

The per-phase initial duty cycle limit and peak current during a

load step are determined by

()

BIAS

MAX

COMP

MAX

−

(32)

(

)

VID

MAX

PHMAX

−

≅

(33)

A type three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 35 to

Equation 39 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3192A section).

ADP3192A Datasheet(PDF) 25 Page - Analog Devices

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