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56F8366 Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc

Part # 56F8366
Description  16-bit Digital Signal Controllers
PDF  184 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

56F8366 Datasheet(HTML) 31 Page - Freescale Semiconductor, Inc

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Signal Pins
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
31
Preliminary
PHASEA1
(TB0)
(SCLK1)
(GPIOC0)
6Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1.
TB0 — Timer B, Channel 0
SPI 1 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. To activate the SPI function, set the
PHSA_ALT bit in the SIM_GPS register. For details, see Part
6.5.8.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8366, the default state after reset is PHASEA1.
In the 56F8166, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.
PHASEB1
(TB1)
(MOSI1)
(GPIOC1)
7Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1.
TB1 — Timer B, Channel 1
SPI 1 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data. To activate the SPI function,
set the PHSB_ALT bit in the SIM_GPS register. For details, see
Part 6.5.8.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8366, the default state after reset is PHASEB1.
In the 56F8166, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description



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