56F8366 datasheet(20/184 Pages) FREESCALE

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56F8366 Technical Data, Rev. 6

Freescale Semiconductor

Preliminary

CLKO

Output

In reset,

output is

disabled

Clock Output — This pin outputs a buffered clock signal. Using

the SIM CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled, CLK_MSTR

(system clock), IPBus clock, oscillator output, prescaler clock and

postscaler clock. Other signals are also available for test purposes.

See Part 6.5.7 for details.

(GPIOA8)

138

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Address Bus — A0 - A5 specify six of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead of

using the default setting.

Port A GPIO — These six GPIO pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, set the appropriate

GPIO bit in the GPIOA_PUR register.

Example: GPIOA8, set bit 8 in the GPIOA_PUR register.

(GPIOA9)

(GPIOA10)

(GPIOA11)

(GPIOA12)

(GPIOA13)

Table 2-2 Signal and Package Information for the 144-Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

56F8366 Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc

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