56F8366 datasheet(71/184 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8366 Technical Data, Rev. 6

Freescale Semiconductor

Preliminary

Table 4-35 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

Address Offset

SIM_CONTROL

Control Register

SIM_RSTSTS

Reset Status Register

SIM_SCR0

Software Control Register 0

SIM_SCR1

Software Control Register 1

SIM_SCR2

Software Control Register 2

SIM_SCR3

Software Control Register 3

SIM_MSH_ID

Most Significant Half JTAG ID

SIM_LSH_ID

Least Significant Half JTAG ID

SIM_PUDR

Pull-up Disable Register

Reserved

SIM_CLKOSR

Clock Out Select Register

SIM_GPS

Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE

Peripheral Clock Enable Register

SIM_ISALH

I/O Short Address Location High Register

SIM_ISALL

I/O Short Address Location Low Register

SIM_PCE2

Peripheral Clock Enable Register 2

Table 4-36 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

Address Offset

LVI_CONTROL

Control Register

LVI_STATUS

Status Register

56F8366 Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

56F8366 Datasheet(HTML) 71 Page - Freescale Semiconductor, Inc

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