56F8366 datasheet(69/184 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8366 Technical Data, Rev. 6

Freescale Semiconductor

Preliminary

Table 4-31 GPIOC Registers Address Map

(GPIOC_BASE = $00 F310)

Address Offset

Reset Value

GPIOC_PUR

Pull-up Enable Register

0 x 07FF

GPIOC_DR

Data Register

0 x 0000

GPIOC_DDR

Data Direction Register

0 x 0000

GPIOC_PER

Peripheral Enable Register

0 x 07FF

GPIOC_IAR

Interrupt Assert Register

0 x 0000

GPIOC_IENR

Interrupt Enable Register

0 x 0000

GPIOC_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOC_IPR

Interrupt Pending Register

0 x 0000

GPIOC_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOC_PPMODE

Push-Pull Mode Register

0 x 07FF

GPIOC_RAWDATA

Raw Data Input Register

—

Table 4-32 GPIOD Registers Address Map

(GPIOD_BASE = $00 F320)

Address Offset

Reset Value

GPIOD_PUR

Pull-up Enable Register

0 x 1FFF

GPIOD_DR

Data Register

0 x 0000

GPIOD_DDR

Data Direction Register

0 x 0000

GPIOD_PER

Peripheral Enable Register

0 x 1FC0

GPIOD_IAR

Interrupt Assert Register

0 x 0000

GPIOD_IENR

Interrupt Enable Register

0 x 0000

GPIOD_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOD_IPR

Interrupt Pending Register

0 x 0000

GPIOD_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOD_PPMODE

Push-Pull Mode Register

0 x 1FFF

GPIOD_RAWDATA

Raw Data Input Register

—

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