56F8366 datasheet(68/184 Pages) FREESCALE

68 / 184 page

56F8366 Technical Data, Rev. 6

Freescale Semiconductor

Preliminary

Table 4-29 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

Address Offset

Reset Value

GPIOA_PUR

Pull-up Enable Register

0 x 3FFF

GPIOA_DR

Data Register

0 x 0000

GPIOA_DDR

Data Direction Register

0 x 0000

GPIOA_PER

Peripheral Enable Register

0 x 3FFF

GPIOA_IAR

Interrupt Assert Register

0 x 0000

GPIOA_IENR

Interrupt Enable Register

0 x 0000

GPIOA_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOA_IPR

Interrupt Pending Register

0 x 0000

GPIOA_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOA_PPMODE

Push-Pull Mode Register

0 x 3FFF

GPIOA_RAWDATA

Raw Data Input Register

—

Table 4-30 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

Address Offset

Reset Value

GPIOB_PUR

Pull-up Enable Register

0 x 00FF

GPIOB_DR

Data Register

0 x 0000

GPIOB_DDR

Data Direction Register

0 x 0000

GPIOB_PER

Peripheral Enable Register

0 x 000F for 20-bit EMI

address at reset.

0 x 0000 for all other cases.

See Table 4-4 for details.

GPIOB_IAR

Interrupt Assert Register

0 x 0000

GPIOB_IENR

Interrupt Enable Register

0 x 0000

GPIOB_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOB_IPR

Interrupt Pending Register

0 x 0000

GPIOB_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOB_PPMODE

Push-Pull Mode Register

0 x 00FF

GPIOB_RAWDATA

Raw Data Input Register

—

56F8366 Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc

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