56F8366 datasheet(52/184 Pages) FREESCALE

52 / 184 page

56F8366 Technical Data, Rev. 6

Freescale Semiconductor

Preliminary

CSOR 1

Chip Select Option Register 1

0x5FAB programmed for

chip select for data space,

word wide, read and write,

11 waits

CSOR 2

Chip Select Option Register 2

CSOR 3

Chip Select Option Register 3

CSOR 4

Chip Select Option Register 4

CSOR 5

Chip Select Option Register 5

CSOR 6

Chip Select Option Register 6

CSOR 7

Chip Select Option Register 7

CSTC 0

$10

Chip Select Timing Control Register 0

CSTC 1

$11

Chip Select Timing Control Register 1

CSTC 2

$12

Chip Select Timing Control Register 2

CSTC 3

$13

Chip Select Timing Control Register 3

CSTC 4

$14

Chip Select Timing Control Register 4

CSTC 5

$15

Chip Select Timing Control Register 5

CSTC 6

$16

Chip Select Timing Control Register 6

CSTC 7

$17

Chip Select Timing Control Register 7

BCR

$18

Bus Control Register

0x016B sets the default

number of wait states to 11

for both read and write

accesses

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

Address Offset

TMRA0_CMP1

Compare Register 1

TMRA0_CMP2

Compare Register 2

TMRA0_CAP

Capture Register

TMRA0_LOAD

Load Register

TMRA0_HOLD

Hold Register

TMRA0_CNTR

Counter Register

TMRA0_CTRL

Control Register

TMRA0_SCR

Status and Control Register

Table 4-10 External Memory Integration Registers Address Map (Continued)

(EMI_BASE = $00 F020)

Address Offset

Reset Value

56F8366 Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc

56F8366 Datasheet(HTML) 52 Page - Freescale Semiconductor, Inc

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