1997 May 30

12

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

FUNCTIONAL DESCRIPTION

The SAA7740H is used as a slave device. The internal

operation is automatically synchronized with the word

to compute a stereo output sample. The external clock

which generate more than 384 clocks cycles will cause the

processor to return to a wait state.

The external clock can be either a crystal connected

directly to the DAPIC, or any clock generated in the system

which contains DAPIC.

DAPIC. The serial clock (DIBCK and DOBCK) and the

word select (DIWS and DOWS) are applied from an

external source. The two inputs and outputs are fully

synchronized. However, the inputs do not have to be

synchronized with the outputs. The clock and word select

signals can be separated at the input and output.

The input and output buses support word lengths in

bits can be read by the DAPIC. Zeros will be added at the

LSB position should less than 20 bits be applied. If more

than 20 bits are applied the extra LSBs will be ignored.

Because the DAPIC is a slave device it can only be

(see Chapter “Timing characteristics” and Fig.9).

the DAPIC for the audio signal processing and write the

coefficients and the external delay line addresses of the

different signal processing algorithms. New coefficients

are updated in real time to the internal RAM.

The transfer byte organization is as follows:

START condition

First byte (8 bits)

Acknowledge (1-bit)

Second byte (8 bits)

Acknowledge (1-bit)

Third to tenth byte (8 bits)

Acknowledge (1-bit)

STOP condition.

addressed. If the device detects its address it answers with

an acknowledge by pulling down the data line (SDA) for

one clock period (SCL line). The second byte contains the

address of the internal RAM to which the first new

coefficient should have written. The data will then be

transmitted. Each new word (coefficient) is 2 bytes wide.

Up to four words of data can be written within one transfer.

Should the mode of the feature register be addressed then

only one data word will be transferred.

bus, the clock has to be generated by the host

microcontroller.

(bus free between a STOP and START condition) should

be:

Where:

Number of coefficients = coeff

t

inv

coeff

1

+

f

as

------------------------



 ms

>

Table 1

Note

1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will

respond with an acknowledge pulse on the SDA line.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

00110

0