SAA7740 datasheet(14/28 Pages) PHILIPS

14 / 28 page

1997 May 30

Philips Semiconductors

Product speciﬁcation

Digital Audio Processing IC (DAPIC)

SAA7740H

DRAM interface

The DRAM interface contains a nibble wide data bus, a

9-bit wide address bus and all necessary control signals to

enable the different DRAM configurations.

Timing of the control signals RAS, CAS, CAS2, A8B, OE

and WE is related to the applied clock frequency of the

DAPIC. The important timing parameters are the page

mode cycle time (tcy;CAS), the access time (tacc;RAS), the

refreshing rate and the maximum value for RAS to CAS

delay time (tdRAS;CAS) (see Chapter “Timing

characteristics” and Fig.10). A read/write operation will

always be executed in the page mode (one row address

and four column addresses) because every data transfer

consists of 4 nibbles.

The refresh time of the DRAM (trfsh) must be greater than;

where ‘addr’ is the number of physical address lines and

fas is measured in kHz.

rfsh

2addr

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For fast DRAMs, the maximum value for RAS to CAS

delay time (tdRAS;CAS) is important.

Different DRAM combinations can be connected to the

DAPIC. The smallest DRAM is a 64

× 4-bit (256 kbits)

RAM. For this configuration, 16K data words can be

stored. When this RAM is connected to the DAPIC, the

MSB address signal (A8) can be felt floating.

The DAPIC can address up to 1 Mbit DRAMs. However,

RAMs greater than 1 Mbit can also be connected. This,

therefore, implies that the redundant address lines of the

RAM must be fixed to VDD or VSS or must be joined with

one of the other address pins.

The choice of a 256 kbit or a 1 Mbit DRAM device must be

indicated by a flag bit residing in the start address control

word of the different delay lines.

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