SAA7740 datasheet(20/28 Pages) PHILIPS

20 / 28 page

1997 May 30

Philips Semiconductors

Product speciﬁcation

Digital Audio Processing IC (DAPIC)

SAA7740H

I2S-BUS PROTOCOL

The I2S-bus digital interface is used for communication to

external digital sources. It is a 3-line serial bus with one

line each for data, clock and word select. Figure 11

illustrates an excerpt from the Philips I2S-bus specification

interface report with respect to general timing and format

of the bus. Word select (WS) at logic 0 signifies the left

channel and logic 1 the right channel.

The serial data is transmitted in two’s complement with

MSB first. One clock period after the negative edge of the

WS line, the MSB of the left channel is transmitted. Data is

synchronized on the negative edge of the clock and

latched on the positive edge.

Two data line have been implemented as input from an

external processor for the four audio channels. Because of

this configuration the DAPIC operates in the following

manner.

The I2S-bus input block reads 4 samples (left and right

samples of the front and rear channel) and stores the

information into the register file. The operators read from

the register file, process the data and store the

intermediate results back into the register file. If a delay

line is required, the external RAM will need to be

accessed. The output samples are read from the register

file and are passed via the fade unit to the I2S-bus output

block. The same operation is repeated for each incoming

audio sample.

Fig.11 I2S-bus timing format.

handbook, full pagewidth

MLC159

SCK

MSB

LEFT

MSB

RIGHT

tHC

t LC

thr

t sr

VIH

VIL

VIH

VIL

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