SAA7740 datasheet(4/28 Pages) PHILIPS

4 / 28 page

1997 May 30

Philips Semiconductors

Product speciﬁcation

Digital Audio Processing IC (DAPIC)

SAA7740H

PINNING

SYMBOL

DESCRIPTION

RST

reset input (active LOW)

SCL

serial clock input (I2C-bus)

SDA

serial data input/output (I2C-bus)

MUTE

mute input (active HIGH)

n.c.

not connected

n.c.

not connected

VDD

supply voltage

VDD

supply voltage

VSS

ground supply

CAS

column address strobe (DRAM)

(active LOW)

input/output data bus line 0 (DRAM)

input/output data bus line 1 (DRAM)

VSS

ground supply

output buffer enable (DRAM)

(active LOW)

input/output data bus line 2 (DRAM)

input/output data bus line 3 (DRAM)

CAS2

second column address strobe

(active LOW)

write enable (DRAM; active LOW)

RAS

row address strobe (DRAM;

active LOW)

A8B

inverse MSB address line output

(DRAM)

address line output 8 (DRAM)

address line output 7 (DRAM)

address line output 6 (DRAM)

address line output 5 (DRAM)

VSS

ground supply

VDD

supply voltage

address line output 4 (DRAM)

address line output 3 (DRAM)

address line output 2 (DRAM)

address line output 1 (DRAM)

address line output 0 (DRAM)

VDD

supply voltage

MUX

address latch strobe output (SRAM)

DO1D

digital audio output 1 (I2S-bus)

DO2D

digital audio output 2 (I2S-bus)

DOWS

digital audio input word select

DOBCK

digital audio input serial bit clock

VDD

supply voltage

n.c.

not connected

VSS

ground supply

DI1D

digital audio input 1 (I2S-bus)

DI2D

digital audio input 2 (I2S-bus)

DIWS

digital audio input word select

DIBCK

digital audio input serial bit clock

TSTCLK

clock input for test mode

(should be tied LOW)

VSS

ground supply

TST1

test pin input 1

(should be tied LOW)

TST2

test pin input 2

(should be tied LOW)

TST3

test pin input 3

(should be tied LOW)

VSS

ground supply

AS1

address select input 1 (I2C-bus)

AS2

address select input 2 (I2C-bus)

VDD

supply voltage

VDD

supply voltage

VSS

ground supply

CLK1/

XTAL1

clock or crystal input

n.c.

not connected

n.c.

not connected

XTAL2

crystal output 2

VDDX

crystal supply voltage

VSSX

crystal ground supply

SCCLK

scan test clock input

(should be tied LOW)

CLKO

clock signal output

ALL

mode select input

(should be tied HIGH)

SYMBOL

DESCRIPTION

SAA7740 Datasheet(PDF) 4 Page - NXP Semiconductors

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