SAF7113 datasheet(43/80 Pages) PHILIPS

43 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Fig.29 Vertical timing diagram for 50 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR

or fast mode (HTC = 01 or 11)].

HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.

ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.

VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = BH.

V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.

VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.

FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.

(1) VREF range short or long can be programmed via I2C-bus bit VRLN.

The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.

The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

(2) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.

(3) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the

field is even. If HREF is inactive during the falling edge of V123, the field is odd. The specific position of the slope is dependent on the

internal processing delay and may change a few clock cycles from version to version.

handbook, full pagewidth

313

314

315

316

317

318

319

335

336

234

567

625

RTS0/1 HREF

input CVBS

(b) 2nd field

(a) 1st field

VRLN = 1(1)

VRLN = 0(1)

RTS0/1 VREF

VRLN = 0(1)

624

623

622

RTS0/1 HREF

input CVBS

312

311

310

337

MHB336

499

× 2/LLC

RTS0/1 VS

RTS0/1 ODD

RTS0/1 V123(3)

RTS0/1 ODD

RTS0/1 FID(2)

320

RTS0/1 VS

RTS0/1 V123(3)

RTS0/1 FID(2)

× 2/LLC

VRLN = 1(1)

RTS0/1 VREF

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