SAF7113 datasheet(66/80 Pages) PHILIPS

66 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

15.2.20 SUBADDRESS 13H

Table 51 Output control SA 13, D7, D4, D3, D1 and D0

Note

1. Analog-to-digital converter selection via MODE3 to MODE0 (subaddress 02H; see Figs 35 to 38).

FUNCTION

BIT

LOGIC LEVEL

DATA BIT

Analog test select (AOSL)

AOUT connected to internal test point 1

AOSL1

AOSL0

AOUT connected to input AD1

AOSL1

AOSL0

AOUT connected to input AD2

AOSL1

AOSL0

AOUT connected to internal test point 2

AOSL1

AOSL0

Field ID polarity if selected on RTS1 or RTS0 outputs if RTSE1, RTSE0 (subaddress 12H) are set to 1111

Default

FIDP

Inverted

FIDP

Selection bit for status byte functionality OLDSB

Default status information; see Table 55

OLDSB

Old status information, for compatibility

reasons; see Table 55

OLDSB

Analog-to-digital converter output bits on VPO7 to VPO0 in bypass mode (VIPB = 1, used for test purposes)

ADLSB; note 1

AD8 to AD1 (MSBs) on VPO7 to VPO0

ADLSB

AD7 to AD0 (LSBs) on VPO7 to VPO0

ADLSB

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