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SAF7113 Datasheet(PDF) 63 Page - NXP Semiconductors |
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SAF7113 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 80 page ![]() 2000 May 08 63 Philips Semiconductors Product specification 9-bit video input processor SAF7113H 15.2.18 SUBADDRESS 11H Table 48 Output control 1 SA 11 FUNCTION BIT LOGIC LEVEL DATA BIT Colour on (COLO) Automatic colour killer COLO 0 D0 Colour forced on COLO 1 D0 YUV decoder bypassed (VIPB) Processed data to VPO output VIPB 0 D1 ADC data to VPO output; dependent on mode settings VIPB 1 D1 Output enable real-time (OERT) RTS0, RTS1, RTCO high-impedance inputs OERT 0 D2 RTS0, RTCO active, RTS1 active, if RTSE13 to RTSE10 = 0000 OERT 1 D2 Output enable YUV data (OEYC) VPO-bus high-impedance OEYC 0 D3 Output VPO-bus active or controlled by RTS1; see Table 19 OEYC 1 D3 Selection of horizontal lock indicator for RTS0, RTS1 outputs Standard horizontal lock indicator (low-passed) HLSEL 0 D4 Fast lock indicator (use is recommended only for high performance input signals) HLSEL 1 D4 General purpose switch [available on pin RTS0, if control byte RTSE03 to RTSE00 (subaddress 12H) is set to 0010] LOW GPSW0 0 D5 HIGH GPSW0 1 D5 CM99 compatibility to SAA7199 (CM99) Default value CM99 0 D6 To be set only if SAA7199 (digital encoder) is used for re-encoding in conjunction with RTCO CM99 1 D6 General purpose switch [available on pin RTS1, if control byte RTS103 to RTS100 (subaddress 12H) is set to 0010] LOW GPSW1 0 D7 HIGH GPSW1 1 D7 |
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