SAF7113 datasheet(61/80 Pages) PHILIPS

61 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

15.2.16 SUBADDRESS 0FH

Table 42 Chrominance gain control SA 0F (D6 to D0)

Table 43 Chrominance gain control SA 0F (D7)

15.2.17 SUBADDRESS 10H

Table 44 Format/delay control SA 10 (D2 to D0)

Clear DTO (CDTO)

Disabled

CDTO

Every time CDTO is set, the internal subcarrier DTO phase is reset to

° and the RTCO output generates a logic 0 at time slot 68 (see

external document

“RTC Functional Description”, available on

request). So an identical subcarrier phase can be generated by an

external device (e.g. an encoder).

CDTO

CHROMINANCE GAIN VALUE

(IF ACGC IS SET TO LOGIC 1)

CONTROL BITS D6 TO D0

CGAIN6

CGAIN5

CGAIN4

CGAIN3

CGAIN2

CGAIN1

CGAIN0

Minimum gain (0.5)

000000

Nominal gain (1.125)

100100

Maximum gain (7.5)

111111

AUTOMATIC CHROMINANCE GAIN CONTROL ACGC

ACGC

Programmable gain via CGAIN6 to CGAIN0

LUMINANCE DELAY

COMPENSATION (STEPS IN 2/LLC)

CONTROL BITS D2 TO D0

YDEL2

YDEL1

YDEL0

−4...

...0...

...3

FUNCTION

CHBW/CSTD

BIT

LOGIC

LEVEL

DATA BIT

50 Hz

60 Hz

SAF7113 Datasheet(PDF) 61 Page - NXP Semiconductors

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