SAF7113 datasheet(55/80 Pages) PHILIPS

55 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

15.2.4

SUBADDRESS 03H

Table 30 Analog control 2 (AICO2) SA 03

15.2.5

SUBADDRESS 04H

Table 31 Gain control analog (AICO3); static gain control channel 1 GAI1 SA 04, D7 to D0

FUNCTION

LOGIC LEVEL

DATA BIT

Static gain control channel 1 (GAI18) (see SA 04)

Sign bit of gain control

see Table 31

Static gain control channel 2 (GAI28) (see SA 05)

Sign bit of gain control

see Table 32

Gain control ﬁx (GAFIX)

Automatic gain controlled by MODE3 to MODE0

Gain is user programmable via GAI1 + GAI2

Automatic gain control integration (HOLDG)

AGC active

0D3

AGC integration hold (freeze)

White peak off (WPOFF)

White peak control active

White peak off

AGC hold during vertical blanking period (VBSL)

Short vertical blanking (AGC disabled during equalization and serration

pulses)

0D5

Long vertical blanking (AGC disabled from start of pre-equalization pulses

until start of active video (line 22 for 60 Hz, line 24 for 50 Hz)

1D5

HL not reference select (HLNRS)

Normal clamping if decoder is in unlocked state

Reference select if decoder is in unlocked state

DECIMAL

VALUE

GAIN

(dB)

SIGN

BIT

CONTROL BITS D7 TO D0

GAI18

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

0...

≈−3

00000000

...117...

≈0

01110101

...511

≈6

11111111

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