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SAF7113 Datasheet(PDF) 56 Page - NXP Semiconductors |
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SAF7113 Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 80 page ![]() 2000 May 08 56 Philips Semiconductors Product specification 9-bit video input processor SAF7113H 15.2.6 SUBADDRESS 05H Table 32 Gain control analog (AICO4); static gain control channel 2 GAI2 SA 05, D7 to D0 15.2.7 SUBADDRESS 06H Table 33 Horizontal sync begin SA 06, D7 to D0 15.2.8 SUBADDRESS 07H Table 34 Horizontal sync stop SA 07, D7 to D0 DECIMAL VALUE GAIN (dB) SIGN BIT (SA 03, D1) CONTROL BITS D7 TO D0 GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 0... ≈−3 0 00000000 ...117... ≈0 0 01110101 ...511 ≈6 1 11111111 DELAY TIME (STEP SIZE = 8/LLC) CONTROL BITS D7 TO D0 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 −128...−109 (50 Hz) forbidden (outside available central counter range) −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) Recommended value for raw data type; see Fig.24 1 1 101001 DELAY TIME (STEP SIZE = 8/LLC) CONTROL BITS D7 TO D0 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 −128...−109 (50 Hz) forbidden (outside available central counter range) −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) Recommended value for raw data type; see Fig.24 0 0 001101 |
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