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MAIN READS FROM SUBORDINATE

WRITE DATA FORMAT

MAIN WRITES TO SUBORDINATE

READ DATA FORMAT

SYNC

DEV ADDR + R/W

REG ADDR

NUMBER OF BYTES

BYTE 1

ACK

BYTE N

MAIN WRITES TO SUBORDINATE

SYNC

DEV ADDR + R/W

REG ADDR

NUMBER OF BYTES

MAIN READS FROM SUBORDINATE

ACK

BYTE 1

BYTE N

Figure 30. GMSL2 UART Protocol for Base Mode

UART Bypass Mode

In Bypass mode, the serializer/deserializer ignore UART commands from the μC, allowing the μC to communicate only

with peripheral devices. The μC cannot access the serializer/deserializer’s registers in this mode. The UART transitions

are simply sent over the GMSL link. Ignoring UART transactions prevents inadvertent misprogramming of serializer and

deserializer registers. The device addresses of the serializer and deserializer in this mode are not programmable.

Switching Between UART Base and Bypass Modes

There are two ways to switch between Base and Bypass mode: programming the register and using the MS pin.

When programmed by register, Bypass mode is only active when there is UART activity. When there is no UART activity

for a selected timeout, both devices exit Bypass mode, and the bit is automatically cleared.

When set by the MS pin, a high pin level puts the device into Bypass mode, and a low level puts the device into Base

mode. MS is set on the fly and is not latched on power-up.

UART Frame Format

Regular UART frames with an even parity bit are used to carry 1 byte of data each. A frame consists of a low start bit

followed by 8 data bits, a parity bit, and is finished with a high stop bit. The parity bit is high if the number of ones in the 8

bits of data is odd; otherwise, the parity bit is low. There must be at least 1 high stop bit. If the next frame is in the same

packet, there can be no more than 4 high bits from the end of the stop bit to the beginning of the next start bit. Note that

in the case of a parity bit error, the packet is discarded, starting from the frame with the error. The start of each frame

is always a high-to-low transition (i.e., the stop bit is high, and the start bit is low). The phase of the internal UART bit

clock is adjusted using the start bit of each frame. The framer calibrates the length of 1 UART bit in terms of the internal

oscillator clock using the synchronization frame (i.e., the first frame of a UART packet transmission). In Bypass mode, the

parity bit is enabled by default, but the frames are not checked for parity errors. Either even or odd parity can be used.

The parity bit is passed along with UART data transmissions, and the recipient of the data must perform error checking.

The parity bit (which is enabled by default in Bypass mode) can be disabled before entering Bypass mode. Note that the

bit rate in Bypass mode must be the same bit rate last used in Base mode.

MAX96751

GMSL2 Serializer with HDMI 2.0 Input

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